1. Field of the Invention
The present invention relates generally to Asynchronous Transfer Mode (ATM) systems and to the design of instructions for processors. More specifically, the present invention relates to a system, method and processor instruction for de-scrambling and bit-order-reversing ATM payload data.
2. Related Art
ATM (Asynchronous Transfer Mode) cell streams are a commonly used way to format and transport data in a digital telecommunication system, for example over an ADSL (Asymmetric Digital Subscriber Line) link. An ATM cell comprises a 5-byte cell header and 48 bytes of payload. The cell header contains address and control data, which is used in a network to direct the transfer of the ATM cell from its source to its destination. The payload contains the data to be communicated to the destination.
International standards for ADSL and other forms of DSL (such as ITU-T Recommendation G992.1 entitled “Asymmetrical digital subscriber line (ADSL) transceivers,” ITU-T Recommendation G992.2 entitled “Splitterless asymmetric digital subscriber line (ADSL) transceivers,” ITU-T Recommendation G992.3 entitled “Asymmetric digital subscriber line transceivers—2 (ADSL2),” and ITU-T Recommendation G992.4 entitled “Splitterless asymmetric digital subscriber line transceivers 2 (splitterless ADSL2)”) define a method of conveying ATM cell streams over the DSL link. The method requires, amongst other things, that as cells are processed in the transmitting modem, the payload data bytes in each transmitted cell are scrambled using a self-synchronizing scrambler with polynomial X43+1. An equivalent way of describing the scrambling process is that for the stream of successive bits making up the input to the scrambler, x(n) (n=0, 1, 2, . . . ), the output of the scrambler y(n) is defined recursively as:y(n)=x(n)+y(n−43)where + means addition modulo 2 (which is equivalent to logical “exclusive-or”). In other words, for each input bit, the output bit is the exclusive-or of that input bit and the output bit from 43 bit-times earlier. This scrambling scheme is also employed in a number of other contexts where ATM streams are passed between processing units over intermediate links.
In the receiving modem, the data must then be de-scrambled by applying the inverse operation to recover the original values of the data bytes which were input to the scrambling process in the transmitting modem. Thus, the de-scrambler should implement the inverse processing to create a de-scrambled sequence z(n), where n—(0,1,2, . . . ), by any means equivalent to:z(n)=y(n)+y(n−43)where again + means addition modulo 2. Unlike the scrambling process, the descrambling process is not recursive—the output bits depend only on current and previous input bits, not on previous output bits. If no corruption of the y(n) sequence has occurred between scrambler and de-scrambler, z(n) will equal x(n) for all n≧43. For n<43, the values of both y(n) and z(n) depend respectively on the initial values of scrambler and de-scrambler versions of the sequence y(m) (m=−43, −42, . . . −1), which is not defined. If y(m) at the receiver=y(m) at the transmitter then z(n) will equal x(n) for all n≧0, but this matching is neither required nor guaranteed by the standards. The fact that the first 43 bits of the de-scrambled bit stream are not reliable is usually considered an unimportant issue in practice.
A further common requirement for transmission of ATM cell streams over a DSL link concerns the ordering of the data bits in each byte of the ATM cell data being sent and received over the DSL link. When cells are passed across the external data interface of a DSL modem, DSL standards require the bits in each byte of the cell to be reversed in order. In other words, whereas externally the most significant bit of each byte is processed first, internally in the modem, the least significant bit of each byte must be processed first, but the actual order of processing of the bits must be preserved throughout. This reversal applies to all bytes of each ATM cell. This bit order reversal is performed in both directions of transfer at the modem's external interface, i.e. both for ATM cells incoming for transmission across the DSL link, and for ATM cells which have been received across the DSL link, to be sent out via the external data interface.
In an ATM-based modem in a telecommunication system, ATM cells may be received by the modem, over the physical link(s) the modem controls, at a high rate. An example of this situation would be in a multi-line ADSL or VDSL modem in a central-office DSL access multiplexer. Because of the high rate, it is important for the modem to be able to de-scramble the payload data of the ATM cells efficiently.
In prior art hardware oriented DSL modems, the de-scrambling of data is typically performed by fixed-function logic circuits. However, such system designs are typically much less adaptable to varying application requirements. In such hardware implementations of the de-scrambling function, the data flow is fixed in an arrangement dictated by the physical movement of data through the hardware, and cannot be adapted or modified to suit different modes of use. For example, in such systems, the ‘state’ (the history of earlier input bits) is held internally within the de-scrambling hardware, rather than being passed in as and when de-scrambling is required. This means that re-using a hardware implementation to de-scramble multiple distinct data streams at the same time is either impossible, or certainly more complex to implement, since some arrangement must be made to allow the individual states for the different streams to be swapped in and out.
Current prior art DSL modems often use software to perform at least some of the various functions in a modem. One disadvantage of de-scramblers in current DSL modems is the inefficiency of such de-scramblers as the line-density and data-rates required of modems increase. As line-density and data-rates increase, so does the pressure on prior art de-scramblers to perform efficiently the individual processing tasks, such as de-scrambling, which make up the overall modem function.
Another disadvantage with current prior art de-scramblers is the software complexity required to implement such de-scramblers. Using conventional bit-wise instructions such as bit-wise shift, bit-wise exclusive-or, etc. may take many tens or even hundreds of cycles to perform the ATM de-scrambling operation for a single ATM cell. One processor may need to handle several hundred thousand ATM cells per second. Thus, the de-scrambling process for each cell can represent a significant proportion of the total computational cost for current prior art DSL modems, especially in the case of a multi-line system where one processor handles the operations for multiple lines. With increasing workloads, it becomes necessary to improve the efficiency of de-scrambling and bit-order-reversing ATM cell payload bytes over that of such prior art modems.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.